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Low power spintronics wireless autonomous node (SWAN) integrated circuits developed via spintronics technology accelerator platform

Project

SWAN-on-chip - Low power spintronics wireless autonomous node (SWAN) integrated circuits developed via spintronics technology accelerator platform


Funding origin:
European
European Union
STRIA Roadmaps:
Connected and automated transport (CAT)
Connected and automated transport
Transport mode:
Road
Road
Transport sectors:
Passenger transport
Passenger transport
Freight transport
Freight transport
Project website:
Duration:
Start date: 01/10/2022,
End date: 30/09/2025

Status: Finished
Funding details:
Total cost:
€3 180 373
EU Contribution:
€3 180 372

Overview

Background & policy context:

One of the central keystones of the digital transformation of society is the Internet of Things (IoT) paradigm, however recent focus has turned to the energy consumption of the billions of IoT sensor nodes. In order for the realization of a 'Green IoT', low-power sensor nodes are essential, to extend node lifetime, reduce carbon footprint and reduce costs. Spintronics is an emerging technology which has been demonstrated for several key functionalities associated with wireless sensor networks, including sensing, energy harvesting, communication, memories and novel processing paradigms.

Objectives:

In SWAN-on-chip a spintronics wireless autonomous node (SWAN) is proposed for low-power edge computing. Three homogeneously CMOS integrated spin-chip modules will be developed and benchmarked in the context of low power IoT nodes (namely magnetic field sensor, wireless power transfer, wake-up receiver) (Objective 1), and these spin-chip modules will be brought together into a SWAN prototype functional demonstrator capable of real world data capture and used for specific end user test cases (i.e. electric vehicles and smart metering) (Objective 2).

As well as developing individual spin-chips, a system-on-chip style SWAN-on-chip concept will be validated, with different spintronic functionalities being interconnected via CMOS, either by using multi-functional spintronic stacks or masking techniques to allow multiple spintronics technologies to be processed on a single CMOS wafer (Objective 3).

In addition, the SWAN-on-chip concept will be used to validate the ‘spintronics technology accelerator’ platform, where the spintronics equivalent circuit models (Spin-EC) and spintronics multi-project wafer (Spin-MPW) will create a European-level pathway for the fabrication of monolithically integrated Spintronic/CMOS technologies required for boosting devices up the spintronics value chain (Objective 3).

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