Smart Power ICs are extensively used in automotive embedded systems due to their unique capabilities to merge low power and high voltage devices on the same chip, at a competitive cost. In such devices, induced electrical coupling noise due to switching of the power stages, when integrating such high voltage (HV) devices with low voltage (LV) functions, is a big issue. During switching, parasitic voltages and currents, consisting of electrons and holes, lead to a local shift of the substrate potential that can reach hundreds of millivolts. This electrical coupling noise can severely disturb low voltage circuits. Such parasitic signals are known to represent the major cause of failure and costly circuit redesign in power integrated circuits. Furthermore, parasitic carrier injections are considerably increased under high temperature operation such as those encountered in automotive applications where this problem is even more severe since these dedicated IC's need to be highly reliable and stable over time. Most solutions are layout dependent and are thus difficult to optimize using available electrical simulator software.
The lack of a model strategy that would enable to simulate accurately the injection of minority carriers in the substrate as part of the HV model, as well as its propagation in the substrate, is one of the main reasons for this critical situation. This lack of a design methodology prohibits an efficient design strategy and fails at giving clear predictions of perturbations in high voltage integrated circuits.
The main objective of this project is to study the parasitic substrate coupling effects and enhance the quality of smart power ICs by diminishing risks related to reliability, safety and durability of fully electrical vehicles.